优盘主控芯片IS917定义

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优盘主控芯片IS917定义


[size=13.6014px]– One Channel data bus by small footprint package
[size=13.6014px]– Up to 8 CEs supported(Die form)
[size=13.6014px]– ECC protect up to 70 bit ( configurable ) by 1K bytes
[size=13.6014px]– 2xnm, 2ynm, 1xnm, 1ynm : SLC / MLC / TLC types NAND Flash supported
[size=13.6014px]– ONFI 2.1 spec. interface supported
[size=13.6014px]– Toggle DDR interface supported
[size=13.6014px]– Compliant with USB 3.0 spec. version 1.0
[size=13.6014px]– Compliant with USB 2.0 spec. backward compatible with USB1.1
[size=13.6014px]– Compliant with USB Mass Storage Class spec. version 1.0
[size=13.6014px]– High performance 8051 with hardware acceleration DMA
[size=13.6014px]– F/W off-load engine embedded
[size=13.6014px]– 1.2V low power consumption design
[size=13.6014px]– LED indicator to show link status and r/w traffic
[size=13.6014px]– Customized VID/ PID with serial number
[size=13.6014px]– Built-in LDO regulator
[size=13.6014px]

[size=13.6014px]

[size=13.6014px]

[size=13.6014px]

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Pin Descriptions
Pin Name	Pin #	Pull up/Down	Attribute	Description
DAT[7]	1	Down	I/O	Flash data bit [7]
DAT[6]	2	Down	I/O	Flash data bit [6]
DAT[5]	3	Down	I/O	Flash data bit [5]
DAT[4]	4	Down	I/O	Flash data bit [4]
VCCQ	5		PWR	3.3V/1.8V IO Power input
DQS	6	Down	I/O	Flash DQS
DVDD12	7		PWR	1.2V Core power input
DAT[3]	8	Down	I/O	Flash data bit [3]
DAT[2]	9	Down	I/O	Flash data bit [2]
DAT[1]	10	Down	I/O	Flash data bit [1]
DAT[0]	11	Down	I/O	Flash data bit [0]
VCC18O	12		PWR	Regulator 1.8V output
AVDD33O	13		PWR	Regulator 3.3V output
VDD5I	14		PWR	Regulator 5V input
GND	15		GND	GND
LXO	16		PWR	LXO
DVDD12	17		PWR	1.2V Core power input
LED_RW	18		I/O	R/W Access LED
DVCC33	19		PWR	3.3V IO Power input
LED_U3	20		I/O	USB Mode LED, tie to GND
MODE[0]	21	Down	I	Test mode pin, tie to GND
MODE[1]	22	Down	I	Test mode pin, tie to GND
MODE[2]	23	Down	I	Test mode pin, tie to GND
RST#	24	Up	I	Reset
GND	25		GND	GND
SS_RXP	26		I/O	USB 3.0 differential receive pin positive
GND	27		GND	GND
SS_RXM	28		I/O	USB 3.0 differential receive pin negative
VCC12A	29		PWR	1.2V analog power input
SS_TXP	30		I/O	USB 3.0 differential transmit pin positive
GND	31		GND	GND
SS_TXM	32		I/O	USB 3.0 differential transmit pin negative
VCC33A	33		PWR	3.3V analog power input
DP	34		I/O	USB 2.0 differential pin plus
DM	35		I/O	USB 2.0 differential pin minus
GND	36		GND	GND
DVDD12	37		PWR	1.2 core power input
WP#	38		O	Flash write protection
CE_3	39		O	Flash chip enable 3
CE_2	40		O	Flash chip enable 2
CE_1	41		O	Flash chip enable 1
CE_0	42		O	Flash chip enable 0
VCCQ	43		PWR	3.3/1.8V IO power
RB#	44	Up	I	Flash Ready / Busy Status
CLE	45		O	Flash Channel Command latch
ALE	46		O	Flash Channel Address latch
WE#	47		O	Flash Channel WE#
RE#	48		O	Flash Channel RE#