1. General Description
The Serial ATA Bridge is a single chip solution for serial and parallel ATA translation. It includes the Serial ATA PHY, Link,
Transport, and parallel ATA (application layer) controller. The main applications are for legacy IDE storage devices connecting to
newer chipset supporting serial ATA, such as the iCH5 south bridge of Intel chipset, and serial ATA IDE storage devices connecting
to traditional IDE south bridge.
The Serial ATA physical, link, and transport layer are compliance to Serial ATA Generation 1, which supports a 1.5Gbps data
rate. The application layer supports both the ATA register command set and PACKET command set, which could drive both the Hard
Disk Drive and ATAPI Optical Storage such as CR-ROM, CD-RW, DVD-ROM, DVD-RW, etc. The serial ATA and application layer
support both device and host operation and could be configured by a simple HOST/DEVICE pin.
This chip is designed by 0.18um CMOS technology and 64-pin TQFP or QFN package.

2. Features
2.1 General
0.18um CMOS technology.
Serial ATA 1.5Gbps (Gen. 1) PHY.
Spread-Spectrum Clock (SSC) technology.
1.8V and 3.3V power system.
25MHz external reference clock.
64-pin TQFP and QFN packages.
2.2 Host Bridge
ATA/ATAPI PIO mode 0 to 4.
ATA/ATAPI Multiple-Word DMA 0 to 2.
ATA/ATAPI Ultra DMA of transfer rate 16.7, 25, 33, 48, 66, 100, 133, and 150MB/s.
ATA/ATAPI master/slave emulation.
ATA/ATAPI PACKET command feature set.
ATA/ATAPI-7 Force Unit Access feature set.
ATA/ATAPI-7 Streaming feature set.
ATA/ATAPI LBA48 addressing mode associated with 2-byte sector count.
Serial ATA power saving modes.
Serial ATA BIST operation.
Serial ATA hot-plug.
SATA II Asynchronous Signal Recovery support.
2.3 Device Bridge
ATA/ATAPI PIO mode 0 to 4.
ATA/ATAPI Multiple-Word DMA 0 to 2.
ATA/ATAPI Ultra DMA of transfer rate 16.7, 25, 33, 48, 66, 100, 133, and 150MB/s.
ATA/ATAPI PACKET command feature set.
ATA/ATAPI–7 Force Unit Access feature set.
ATA/ATAPI-7 Streaming feature set.
ATA/ATAPI LBA48 addressing mode associated with 2-byte sector count.

Serial ATA power saving modes.
Serial ATA BIST operation.
Serial ATA hot-plug.
SATA II Asynchronous Signal Recovery support.

3.1 Physical Layer
The physical layer provides serialization/de-serialization transformation between serial data bus and link layer. It also includes
an OOB block to detect COMRESET/COMINIT and COMWAKE for serial bus power on initialization and hot-plug.

3.2 Link Layer
The link layer performs frame envelope encoding and decoding. It receives the frame instruction from transport layer, and
generates the necessary primitive for serial link flow control. While receiving data, it detects the primitive and performs the front-end
operation to extract the useful frame data for transport layer. It also generates CRC for serial link error handling, and provides 8b/10b
data scramble for data transfer.
3.3 Transport Layer
The transfer layer performs frame information structure assembly and decomposition. It also includes FIFO to adjust the speed
mismatch between application layer and serial link.
3.4 Application Layer
The application layer is essentially an ATA/ATAPI protocol engine, which complies with ATA/ATAPI-7. It performs the
protocol and timing control for parallel ATA and ATAPI command set.

5.1 Pin Type Definition
Pin Type Definition
A Analog
D Digital
I Input
O Output
IO Bi-directional
L Internal weak pull-low (Typical 31 KΩ)
H Internal weak pull-high (Typical 31 KΩ)

JM20330 dataSheet for data recovery

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